module Sys_Rst(
    input       clk,
    input       rst,
    output      sys_rst
);

reg     rst_r0;
reg     rst_r1;

always @(posedge clk or posedge rst)begin
    if(rst)begin
        rst_r0 <= 1'b1;
        rst_r1 <= 1'b1;
    end
    else begin
        rst_r0 <= 1'b0;
        rst_r1 <= rst_r0;
    end
end

assign  sys_rst = rst_r1;

endmodule